Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■System port
Applies to all models
Explanation o The system port consists of 16 input signal lines and 8 output
signal lines, and is used to obtain the DIP switch, RS-232C signal line,
memory parity error status, turn the buzzer on/off, and select the cause of
RS-232C interrupts.
o The system port uses one 8255A (or equivalent).
o The I/O addresses used by the system port are as follows.
------------+-------+-----+--------------------------------------------------
I/O address | width | R/W | contents
------------+-------+-----+--------------------------------------------------
0031h | BYTE | R/W | 8255A PORT A read/write data
0033h | BYTE | R/W | 8255A PORT B read/write data
0035h | BYTE | R/W | 8255A PORT C read/write data
0037h | BYTE | W | 8255A control register
------------+-------+-----+--------------------------------------------------
Related I/O 0030h
I/O 0032h
I/O 0050h
I/O 0052h
I/O 0031h
Name 8255A PORT A read/write data
Target All models
Chip Equivalent to 8255A
Function
[READ] PORT A Read
bit 7: DIP SW 2-8
bit 6: DIP SW 2-7
bit 5: DIP SW 2-6
bit 4: DIP SW 2-5
bit 3: DIP SW 2-4
bit 2: DIP SW 2-3
bit 1: DIP SW 2-2
bit 0: DIP SW 2-1
1 = OFF
0 = ON
[WRITE] PORT A Write
■[PC-98LT･HA,PC-H98,PC-9821Ap･As･Ae excepted]
No operation (set to mode 0 input)
■[PC-98LT･HA,PC-H98,PC-9821Ap･As･Ae]
Sets the value of PORT A [Undocumented]
Explanation o Indicates the state of DIP SW 2 on the PC-9800 main unit.
o Some models have some or all of the DIP switches as software DIP switches,
but the setting status can be read from this port just like models with
hardware DIP switches.
o On the PC-98XA, the names of the DIP switches connected to this port are DIP SW 1-1 to 1-8.
o On the PC-98LT/HA, only bit 4 is used. The status of bit 4 can be changed
with switch.exe on the PC-98LT, and in the PC-98HA in the system menu
(launched with CTRL+GRPH+HELP).
o On models other than PC-98LT/HA, PC-H98, and PC-9821Ap/As/Ae, set PORT A of
the 8255A to "Mode 0 Input".
u On PC-98LT/HA, PC-H98, and PC-9821Ap/As/Ae, set PORT A of the 8255A to Mode
0 Output. Used as 8-bit RAM to hold the status of DIP SW 2. At startup, the
software DIP SW settings are written from the backed up memory to PORT A.
On these models, PORT A is always writable, so if it is carelessly rewritten,
the DIP SW 2 setting will not be read correctly.
o PC-98LT-HA stores the software DIP SW settings in memory switch 10h.
Normally it shows 111x0011b. Bit 4 can be changed by the user.
Related DIP SW 2-1 to 2-8
I/O 0033h
Name 8255A PORT B Read data
Target All models
Chip Equivalent to 8255A
Function
[READ] PORT B Read
bit 7: CI# - Status of RS-232C CI signal line ■ [Except for the first generation PC-9801]
1 = OFF
0 = ON
* Undefined on the first generation PC-9801
Related I/O 0030h,0032h
bit 6: CS# - Status of RS-232C CS signal line
1 = OFF
0 = ON
Related I/O 0030h,0032h
bit 5: CD# - Status of RS-232C CD signal line
1 = OFF
0 = ON
Related I/O 0030h,0032h
bit 4: INT3 - Status of INT3 signal line of expansion bus ■ [Normal]
1 = INT3 signal is active
0 = INT3 signal is inactive
Related INT 11h
bit 3: CRTT - CRT type ■ [Normal]
1 = High resolution (DIP SW 1-1 ON)
0 = Standard resolution (DIP SW 1-1 OFF)
* Fixed to 1 on high-resolution compatible machines, PC-H98, laptops,
notebooks, and other models without digital RGB output, as standard
resolution displays cannot be used.
Related I/O 006Eh
DIP SW 1-1
bit 4,3: SHUT0,1 ■ [High resolution]
* Connected to system port PORT C bit 7,5. Some parts of the technical data
book state that it is used in combination with INT3 and CRTT, but it appears
that it always functions as SHUT0,1 when in high-resolution mode.
Related I/O 0035h bit 7,5
bit 2: IMCK - Parity error status in the internal memory
1 = Yes
0 = No
Related I/O 0050h,0052h
INT 02h
bit 1: EMCK - Parity error status in memory added to the expansion slot
1 = Yes
0 = No
Related I/O 0050h,0052h
INT 02h
bit 0: CDAT - Calendar clock read data
* For reading the calendar clock LSI data out terminal
Related I/O 0020h
[WRITE] PORT B write
No operation
Explanation o Set PORT B of the 8255A to mode 0 input and use it.
o On the PC-H98, if you read this port when a parity error occurs, bits 2,1 will be cleared.
Related I/O 98F0h
I/O 0035h
Name 8255A PORT C Read/Write data
Target All models
Chip Equivalent to 8255A
Function
[READ/WRITE] PORT C Read/Write
bit 7: SHUT0 - Shutdown flag 0■[Machines with CPUs after 80286]
Related I/O 0033h bit 4
I/O 00F0h
bit 6: PSTBM - Masks the printer's PSTB# signal■[Other than the first generation PC-9801]
1 = Mask
0 = Do not mask
* Unused on the first generation PC-9801. Controlled by I/O 0094h bit 4.
Related I/O 0094h bit 4
bit 5: SHUT1 - Shutdown flag 1■[Machines with 80286 or later CPU]
Related I/O 0033h bit 3
I/O 00F0h
bit 5: ROM drive write enable■[PC-98LT･HA] ■Undocumented
1 = ROM drive write enable
0 = ROM drive write disable
Related INT 1Fh - Function 95h
bit 4: MCHKEN - RAM parity check
1 = Enable
0 = Disable
* Not used on PC-9801U.
On PC-H98, always operates the same as 1.
Related I/O 0050h,0052h,98F0h
bit 3: BUZ - Buzzer
1 = Stop
0 = Sound
* Turns the built-in beep sound on and off.
Related I/O 0073h,3FDBh
bit 2: TXRE - RS-232C interrupt request by 8251A TXRDY
1 = Yes
0 = No
Related I/O 0030h,0032h
bit 1: TXEE - RS-232C interrupt request by 8251A TXEMPTY
1 = Yes
0 = No
Related I/O 0030h,0032h
bit 0: RXRE - RS-232C interrupt request by 8251A RXRDY
1 = Yes
0 = No
Related I/O 0030h,0032h
Explanation o Set PORT C of 8255A to mode 0 output and use. It is also
possible to set/reset each bit by giving a command to I/O 0037h (control register).
o For machines with 80286 or later CPUs, the behavior after output to I/O
00F0h changes depending on the state of the SHUT0 and SHUT1 ports in bits 7 and 5.
-----+-----+---------------------------------------------------
SHUT0|SHUT1|Behavior
-----+-----+---------------------------------------------------
1 | 1 | Reset behavior (ITF and BIOS perform initialization)
-----+-----+---------------------------------------------------
1 | 0 | Setting prohibited (displays SYSTEM SHUTDOWN on the screen and stops)
-----+-----+---------------------------------------------------
0 | X | Continues program execution after CPU reset.
| | Since ITF performs the following processing, the user program
| | PUSHes the return address in advance and then saves SS:SP to 0000:0404h (DWORD).
| | SS←[0000:0406h]
| | SP←[0000:0404h]
| | RETF
-----+-----+---------------------------------------------------
Related
I/O 0037h
Name Control register
Function
[READ] None
[WRITE] Write control register
[List of control commands for PORT C (I/O 0035h) bits 0 to 7]
-------------+---------------------------------------------------------------
Output value | Operation
-------------+---------------------------------------------------------------
00h,01h | Interrupt request by RXRDY of 8251A of RS-232C 00h=No, 01h=Yes
02h,03h | Interrupt request by TXEMPTY of 8251A of RS-232C 02h=No, 03h=Yes
04h,05h | Interrupt request by TXRDY of 8251A of RS-232C 04h=No, 05h=Yes
06h,07h | Buzzer 06h=Ring, 07h=Stop
08h,09h | RAM parity check 08h=Disabled, 09h=Enabled
0Ah,0Bh | SHUT1 0Ah=0,0Bh=1
0Ch,0Dh | Mask the printer's PSTB# signal 0Ch=Do not mask,0Dh=Mask
0Eh,0Fh | SHUT0 0Eh=0,0Fh=1
-------------+---------------------------------------------------------------
Explanation o 8255A control register. Mode settings and bit-by-bit operation
of PORT C (I/O 0035h) can be performed. For details, see the 8255A data sheet.
Related